As semiconductor ingetrated circuits (ICs) are made with still smaller features, control over processing parameters becomes both more difficult and critical. For example, the permissible variations in device feature sizes become smaller as the feature sizes are reduced. Other examples will be readily apparent to those skilled in the art.
Integrated circuits are typically manufactured by exposing selected portions of a resist, which covers an underlying substrate, to radiation. The resist is then developed, and depending upon whether the resist is positive or negative, the exposed or unexposed portions of the resist are removed. The resist patterns are transferred into the substrate material using such processes as dry etching or ion implantation to thereby form the IC device features. The term "substrate" is used by us to mean the material underlying the resist.
In general, the dimensional control over IC device features is dependent on control of both the lateral dimensions and the profiles, i.e., line edge shapes, of the resist features. While the reason for the dependence on the lateral resist dimensions is obvious, the reason for the dependence on resist profiles is subtle and depends on the precise pattern transfer process used. Thus, it is important to be able to examine not only the lateral dimensions of resist features, but also their profiles, especially at or near the resist-substrate interface. Unfortunately, examination of the resist profiles of features which are either enclosed or near other features, is difficult and may require the destruction of the wafer.
The examination of holes in resists, used to form electrical contacts within the IC, is especially difficult when such holes have lateral dimensions less than 1.0 .mu.m and are defined in resist with a typical thickness greater than 1.0 .mu.m. In order to ensure that the holes are etched into the substrate material immediately under the resist, typically an oxide, with the proper dimensions, it is usually necessary to determine that the profiles forming the holes in resist are close to vertical, that there is no resist remaining at the bottom of the holes, and that the dimensions at the bottoms of the holes are within prescribed limits. If these conditions on the resist features are not met, the pattern transfer will be imperfect and serious loss in device yield will occur, resulting in unwanted expenses.
There are two examination techniques generally used within the IC fabrication industry at the present time. Optical techniques are generally satisfactory for contact windows with diameters greater than 2.0 .mu.m. However, windows smaller than 2.0 .mu.m in diameter generally have an aspect ratio, i.e., ratio of window diameter to resist thickness, comparable to the numerical aperture, typically approximately 0.9, of the microscope objective lens used to observe the holes. Consequently, it is difficult to interpret the optical image when focusing below the top of the hole and examination of the bottom of the hole is impractical.
Techniques using scanning electron microscopes (SEMs) offer better performance than do optical techniques because the use of shorter wavelength radiation allows the use of much smaller numerical apertures. Both high and low voltage SEMs are presently used for IC examination.
High voltage, approximately 20 KeV, SEMs give excellent micrograph images of resist features but generally require deposition of a conductive coating on the wafer to avoid the deleterious effects of charging. Optimized micrographs can be used to determine the dimensions of the contact windows in resist. However, if, as is frequently the case, the aspect ratio of such windows exceeds unity, it is necessary to mechanically cleave the substrates and examine window cross-sections for unambiguous results.
Low voltage SEMs can be used to examine resist samples without a conductive coating, but with a loss of image contrast. The best results are obtained with the wafer tipped almost 40.degree. from the incident electron beam. The tilting, which minimizes charging, is not possible when examining high aspect ratio contact windows because the bottom of the contact window is obscured. Mechanical cleavage of the wafer to reveal window cross-sections is the standard procedure if unambiguous results are desired.
However, mechanical cleaving has several major disadvantages in practice. Some disadvantages relate to cost. The procedure destroys the wafers and it is thereby costly. Preparation of cleaved wafers can be especially lengthy and, therefore, costly, if the IC does not have a regular array of contact windows to cleave through. Most logic array chips are of this type. The lengthy cleaving procedure can delay the manufacturing process until results are obtained, with a cost increment. Additionally, the procedures discussed do not automatically provide for a suitable metric, within the field of view of the examination system, for calibration purposes. This reduces the accuracy of measurement, since it relies on prior calibration of the SEM under observation conditions that are frequently not precisely duplicated during the examination. Precise measurement is therefore difficult because surface charging conditions and details of the beam focus can alter the calibration.